When Taiwan Semiconductor Manufacturing Company first announced the development of its N2 (2 nm-class) manufacturing method in 2020, it didn’t give many details about the node or specify when it planned to start producing it. The business acknowledged this week that the technology is based on a revolutionary transistor structure, but chips using it would not be ready until 2026.
TSMC’s chief executive, C.C. Wei, revealed this week that the company’s N2 node will use gate-all-around (GAA) transistors, as planned (though he did not elaborate on details or reveal the marketing name of the architecture). The fabrication method will continue to use existing 0.33 numerical aperture extreme ultraviolet (EUV) lithography.
By the end of 2024, the technology should be ready for risk production, and by the end of 2025, it should be ready for high-volume manufacture (HVM). This suggests that the first N2-based chips will be delivered to TSMC customers in 2026.
The deployment of new process technologies at TSMC is slowing in general. TSMC has traditionally started production with a brand-new node every two years. N7 began ramping in April 2018, N5 entered HVM in April 2020, and N3 would be used for commercial production only in the second part of 2022, according to TSMC. We should expect an even longer cadence with N2, as the technology will only scale up to around the end of 2025.
The N2 scheduling at TSMC has always been a bit of a puzzle. When the business first announced N2, it simply stated that the new technology would be implemented at a brand-new facility at Baoshan, Hsinchu County, Taiwan. The site (dubbed Fab 20 by others) will house a new fab that will be completed in four phases. The project was approved by Taiwanese authorities in mid-2021, and it was then that we learned that construction would begin in early 2022, giving us our first clues regarding TSMC’s N2 plans.
The fab’s construction was approved by TSMC’s board of directors in early 2022, thus construction should be underway in some form by now. If this is correct, the shell should be finished by the middle of 2023, and the equipment should be installed and ready for production by the second part of 2024. N2 technology and the new fab should be available for HVM in late 2025, after TSMC and its partners finish all necessary preparations (e.g., risk production phase).
Modern production techniques have extremely long cycle times (well over three months), therefore TSMC will have to wait several months before delivering the first batch of 2 nm chips to its alpha customer(s), which is expected to happen in 2026.
While the release date for TSMC’s N2 has been a closely guarded secret, the company has stated that it is aiming for a very mature node with predictable yield and tangible benefits over previous-generation nodes (e.g., N3 derivatives). TSMC anticipates its first Generation GAA-based node to be the best fabrication process when it ramps in the second half of 2025, despite being two or three years behind Samsung Foundry in gate-all-around transistors.
While the release date for TSMC’s N2 has been a closely guarded secret, the company has stated that it is aiming for a very mature node with predictable yield and tangible benefits over previous-generation nodes (e.g., N3 derivatives). TSMC anticipates its first Generation GAA-based node to be the best fabrication process when it ramps in the second half of 2025, despite being two or three years behind Samsung Foundry in gate-all-around transistors.
This year, Samsung Foundry will begin employing GAA transistors in its 3GAE (3nm gate-all-around early) production method. Samsung’s early nodes are normally exclusively utilized internally, so widespread adoption of the new transistor structure won’t happen until 2023, when the contract chipmaker launches its 3GAP (3 nm gate-all-around plus) node for internal and external clients.
Meanwhile, Intel plans to employ ASML’s Twinscan EXE scanners and High-NA EUV lithography with a 0.55 numerical aperture for its 20A node in 2024, followed by ASML’s Twinscan EXE scanners and High-NA EUV lithography with a 0.55 numerical aperture for its 18A node in 2025. Intel wants to adopt a new transistor design and lithography technology in around two years, which is a fairly aggressive timeframe.
TSMC feels that the FinFET transistor structure will suffice for a few more years, hence it is not investing in GAA transistors at this time. By 2025, the business will have six years of expertise with ASML’s Twinscan NXE 0.33 NA EUV tools, making the transition to a new transistor architecture far less dangerous.
TSMC is a cautious company in general. To meet the needs of Apple, the firm’s key customer, which releases new smartphone system-on-chips (SoC) every year, the company must deliver a new node with certain enhancements every year. Meanwhile, in order to suit the needs of firms such as AMD and Nvidia, TSMC creates special versions of its nodes that are optimized for very high performance (N4X) or a mix of transistor density, performance, and power consumption that is beneficial for certain applications (5N, 12N).
